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publications

  1. P.Gillingham, "Strays Insensitive Switched Capacitor Biquads with Reduced Number of Capacitors", Electronics Letters, vol.17, no.4, Feb.19, 1981, p.171-173.

  2. P.Gillingham, "Switched Capacitor Biquadratic Filters", unfinished and unpublished article, Jul.16, 1981.

  3. P.Gillingham, "Frequency Domain Analysis of Switched-Capacitor Networks Using Analog Two-Port Equivalents", AGEN Mitteilungen, no.31, Oct.1981, p.17-24.

  4. P.Gillingham, "Switched Capacitor Circuits for VLSI: A Design Study (Master's Thesis)", Carleton University Department of Electronics Technical Report No. CERL 83-02, Jan.1983

  5. P.Gillingham, "Stray-Free Switched-Capacitor Unit-DelayCircuit", Electronics Letters, vol.20, no.7, Mar.29, 1984, p.308-310.

  6. K.Buttle, G.Aasen, R.Colbeck, R.Gervais, P.Gillingham, D.Ribner, "A 160kb/s Full-Duplex Echo-Cancelling Transceiver", International Solid State Circuits Conference (ISSCC), New York, Feb.13-15, 1985, p.152-153.

  7. R.Colbeck, P.Gillingham, "A 160kb/s Digital Subscriber LoopTransceiver with Memory Compensation Echo Canceller", IEEE Journal of Solid State Circuits, Feb.1986, vol.SC-21, no.1, p.65-72. (reprinted in "Analog MOS Integrated Circuits, II", ed. Paul Gray et al., IEEE Press Selected Reprint Series, 1989, p.401-408.)

  8. P.Gillingham, D.Kirkey, G.Kuhn, C.Kurowski, G.Reesor, M.Skubnik, "Digital Telephone for ISDN Networks with DSP Hands-Free", accepted for European Solid State Circuits Conference (ESSCIRC), Delft, Sep.16-18, 1986, but withdrawn.

  9. R.Colbeck, P.Gillingham, "Analog Design Techniques for a Subscriber Loop Transceiver", European Solid State Circuits Conference (ESSCIRC), Delft, Sep.16-18, 1986, p.128-130.

  10. P.Gillingham, D.Kirkey, J.Erkku, "An ISDN S-Interface Transceiverwith Analog Timing Recovery", International Solid State Circuits Conference (ISSCC), San Francisco, Feb.17-19, 1988, p.108-109.

  11. P.Gillingham, R.C.Foss, V.Lines, G.Shimokura, T.Wojcicki, "High-Speed, High-Reliability Circuit Design for Mega-bit DRAM", IEEE Journal of Solid State Circuits, Aug.1991, vol.SC-28, no.8.  

  12. R.C.Foss, G.Allan, P.Gillingham, F.Larochelle, V.Lines, G.Shimokura, "Application of a High-Voltage Pumped Supply for Low-Power DRAM", 1992 Symposium on VLSI Circuits (Seattle), Jun.4, 1992, p.106-107.

  13. P.Gillingham, B. Hold, I. Mes, C. O'Connell, P. Schofield, K. Skjaveland, R. Torrance, T. Wojcicki, H. Chow, "A 768k Embedded DRAM for1.244Gb/s ATM Switch in a 0.8mm Logic Process", International Solid State Circuits Conference (ISSCC), San Francisco, Feb.8-10, 1996, p.262-263.

  14. P.Gillingham, "A Sense and Restore Technique for Multi-LevelDRAM", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Jul. 1996, vol.CAS-43, no.7, p.483-486.       

  15. R.Torrance,  I.Mes,  B.Hold, D.Jones, J.Crepeau, P.DeMone, D.MacDonald, C.O'Connell, P.Gillingham, R.White, S.Duggins, D.Fielder, "A 33GB/s 13.4Mb Integrated Graphics Accelerator and Frame Buffer", International Solid State Circuits Conference (ISSCC), San Francisco, Feb. 5-7, 1998, p.340-341.

  16. P.Gillingham, B.Vogley, "SLDRAM: High-Performance, Open-Standard Memory", IEEE Micro, Nov./Dec. 1997, vol. 17, no. 6, p.29-39. (translated into Japanese and published in Nikkei Electronics in 2 parts; March 9, 1998, p.177-186; March 23, 1998, p.175-183.)

  17. R.C.Foss, J.Wu, J.Benzreba, G.Valcourt, P.Vlasenko, Y.Wang, P.Gillingham, "Re-Inventing the DRAM for Embedded Use - A Compiled,Wide-Databus DRAM Macrocell with High Bandwidth and Low Power", Custom Integrated Circuits Conference (CICC), Santa Clara, May 1998, p.283-286.

  18. P.Gillingham, "A Choice for Future Mainstream Memory is Clear", Computer Design, June 1998, p.106-108 

  19. P. Gillingham,  "Evolution of DRAM", Memory Design Workshop,1998 Symposium on VLSI Circuits (Honolulu), June 10, 1998 (updated version from 2004 with die photos in colour)

  20. J. Wu, L. Paris, J. Stender, I. Harrison P. DeMone, B. Millar, J. Benzreba, P.Gillingham, "An SDRAM Interface for Simplified At SpeedTesting of the SLDRAM Internal Array", IEEE International Workshop on Memory Technology, Design and Testing, August 24, 1998.

  21. L.Paris, J.Benzreba, P.DeMone, M.Dunn, L.Falkenhagen, P.Gillingham, I.Harrison, W.He, D.MacDonald, M.MacIntosh, B.Millar, K.Wu, H.-J.Oh, J.Stender, V.Chen, J.Wu, "An 800MB/s 72Mb SLDRAM with Digitally Calibrated DLL", International Solid State Circuits Conference (ISSCC), San Francisco, Feb. 15-17, 1999, p.414-415.

  22. B.Millar, P.Gillingham, "Two High-Bandwidth Memory Bus Structures", IEEE Design and Test of Computers, January-March 1999, p.42-52.

  23. P.Gillingham, "Embedded DRAM for Networking Applications", NSC-NRC Workshop on SoC, National Chiao Tung University, Hsinchu, Taiwan, Sept. 14 2000.

  24. P.Gillingham, “Overcome Traditional Memory Speed Barriers with Embedded DRAM”, Electronic Design, June 18, 2001, p.92-98.

  25. P.Gillingham, “Unleashing the Power of Embedded DRAM”, Proceedings of IP/SOC 2004, Grenoble, Dec. 8-9, 2004, p.231-235.

  26. P.Gillingham, "DDR SDRAM Roadmap and an Overview of DDR3", SOC Design Forum, Herzliya, Santa Clara, Hsinchu, Shanghai, Tokyo, Feb.-Mar. 2007. 

  27. J.-K. Kim, H.-B. Pyeon, H.-J. Oh, R. Schuetz, P.Gillingham, “Low Stress Program and Single Wordline Erase Scheme for NAND Flash Memory”, IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, Aug. 26-30, 2007, p.19-20.

  28. R. Schuetz, H.-J. Oh, J.-K. Kim, H.-B. Pyeon, S. Przybylski, P.Gillingham, “HyperLink NAND Flash Memory Architecture for Mass Storage Applications” (invited paper), IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, Aug. 26-30, 2007, p.3-4.

  29. P.Gillingham, "HLNAND: A New Standard for High Performance Flash Memory", Flash Memory Summit, Santa Clara, California, August 2008.

  30. P. Gillingham, J.-K. Kim, R. Schuetz,H.-B. Pyeon, H.-J. Oh, D. Macdonald, E. Choi, D. Chinn, “A 256Gb NAND Flash Memory Stack with 300MB/s HLNAND Interface Chip for Point-to-Point Ring Topology”, International Memory Workshop (IMW), Monterey, May 23-25, 2011.

  31. P. Gillingham, D. Chinn, E. Choi,  J.-K. Kim, D. Macdonald, H.-J. Oh, H.-B. Pyeon, R. Schuetz, “800MB/s NAND Flash Memory Multi-Chip Package with Source-Synchronous Interface for Point-to-Point Ring Topology”, IEEE Access, Dec. 11, 2013.