- R.Colbeck, P.Gillingham, "Decimating Filter", US Pat.4,653,017
- P.Gillingham, "Switched Capacitor Finite Impulse Response Filter", US Pat. 4,751,666
- J.Erkku, P.Gillingham, "Analog Phase Locked Loop", US Pat. 4,803,705
- R.Colbeck, P.Gillingham, "Jitter-Invariant Switched Capacitor Pulse Shaper", US Pat. 5,020,681
- P.Gillingham, "Bandgap Voltage Generator", US Pat. 5,144,223
- P.Gillingham, "Transition Detection Circuit", US Pat. 5,198,708
- R.Foss, P.Gillingham, R.Harland, V.Lines, "High Voltage Boosted Word Line Supply Charge Pump Regulator for DRAM", US Pat. 5,267,201
- P.Gillingham, "Method of Multi-Level Storage in DRAM", US Pat. 5,283,761
- G.Shimokura, P.Gillingham, "DRAM Column Address Latching Technique", US Pat. 5,305,283
- R.Foss, P.Gillingham, R.Harland, V.Lines, "High Voltage Boosted Word Line Supply Charge Pump Regulator for DRAM", US Pat. 5,406,523
- R.Foss, P.Gillingham, R.Harland, M.Mitsuhashi, A.Wada, "Dynamic Random Access Memory Using Imperfect Isolating Transistors", US Pat. 5,414,662
- P.Gillingham, "Column Redundancy Scheme for DRAM Using Normal and Redundant Column Decoders Programmed with Defective Array Address and Defective Column Address", US Pat. 5,469,401
- P.Gillingham, "Method of Multilevel DRAM Sense and Restore", US Pat. 5,532,955
- P.Gillingham, "RAM Variable Size Block Write", US Pat. 5,546,350
- R.Foss, P.Gillingham, R.Harland, M.Mitsuhashi, A.Wada, "Method for DRAM Sensing Current Control", US Pat. 5,574,681
- K.Skjaveland, P.Gillingham, "Memory Cell and Wordline Driver for Embedded DRAM in ASIC Process", US Pat. 5,600,598
- P.Gillingham, "Method of Multilevel DRAM Sense and Restore", US Pat. 5,612,912
- P.Gillingham, R.Torrance, "DRAM Page Copy Method", US Pat. 5,625,601
- D. Fielder, J. Derbyshire, P.Gillingham, R. Torrance, C. O'Connell, "Single Chip Frame Buffer and Graphics Accelerator", US Pat. 5,694,143
- K.Skjaveland, P.Gillingham, "Memory Cell and Wordline Driver for Embedded DRAM in ASIC Process", US Pat. 5,694,355
- R.Foss, P.Gillingham, R.Harland, V.Lines, "High Voltage Boosted Word Line Supply Charge Pump and Regulator for DRAM", US Pat. 5,699,313
- P.Gillingham, "Column Redundancy Scheme for DRAM Using Normal and Redundant Column Decoders Programmed with Defective Array Address and Defective Column Address", US Pat. 5,708,619
- P.Gillingham, "Flexible DRAM Array", US Pat. 5,712,823
- D.Fielder, J.Derbyshire, P.Gillingham, R.Torrance, C.O'Connell, "Memory Devices", US Pat. 5,715,200
- P.Gillingham, "Flexible DRAM Array", US Pat. 5,724,286
- R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 5,796,673
- R.Foss, P.Gillingham, R.Harland, V.Lines, "High Voltage Boosted Word Line Supply Charge Pump and Regulator for DRAM", US Pat. 5,828,620
- J.Wu, L.Chen, P.Gillingham, "Precharge Enabled Self Bootstrapping Wordline Driver for an Embedded DRAM", US Pat. 5,835,438
- P.Gillingham, J.Wu, "Integrated Circuit with Non-Binary Decoding and Data Access", US Pat. 5,854,763
- P.Gillingham, "Flexible DRAM Array", US Pat. 5,903,511
- J.Wu, L.Chen, P.Gillingham, "Precharge Enabled Self Bootstrapping Wordline Driver for an Embedded DRAM", US Pat. 5,923,596
- R.Foss, P.Gillingham, R.Harland, V.Lines, "High Voltage Boosted Word Line Supply Charge Pump and Regulator for DRAM", US Pat. 6,055,201
- J.Wu, L.Chen, P.Gillingham, "Precharge Enabled Self Bootstrapping Wordline Driver for an Embedded DRAM", US Pat. 6,058,050
- R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 6,067,272
- P.Gillingham, “Read/Write Timing for Maximum Utilization of Bidirectional Read/Write Bus”, US Pat. 6,088,774
- P.Gillingham, “BIST Memory Test System”, US Pat. 6,182,257
- P.Gillingham, “Method of Multi-Level Storage in DRAM and Apparatus Thereof”, US Pat. RE37,072
- R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 6,205,083
- R.Foss, P.Gillingham, R.Harland, V.Lines, "High Voltage Boosted Word Line Supply Charge Pump and Regulator for DRAM", US Pat. 6,236,581
- D.James, B.Millar, C.O’Connell, P.Gillingham, B.Keeth, “Method for Transferring Data Associated with a Read/Write Command between a Processor and a Reader Circuit Using a Plurality of Clock Lines”, US Pat. 6,249,827
- P.DeMone, P.Gillingham, “Variable Length Pipeline with Parallel Functional Units”, US Pat. 6,266,750
- R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 6,314,052
- V.Lines, P.Gillingham, A.Ahmed, T.Wojcicki, “Dynamic Content Addressable Memory Cell”, US Pat. 6,320,777
- R.Foss, P.Gillingham, R.Harland, M.Mitsuhashi, A.Wada, "Dynamic Random Access Memory Using Imperfect Isolating Transistors", US Pat. RE37,641
- D.Gustavson, D.James, H.Wiggers, P.Gillingham, C.O’Connell, B.Millar, J.Crepeau, K.Ryan, T.Lee, B.Keeth, T.Manning, D.North, D.Rhoden, H.Stracovsky, Y.Morooka, “Memory System having Synchronous Link DRAM (SLDRAM) Devices and Controller”, US Pat. 6,442,644
- V.Lines, P.Gillingham, A.Ahmed, T.Wojcicki, “Dynamic Content Addressable Memory Cell”, US Pat. 6,483,733
- D. Fielder, J. Derbyshire, P.Gillingham, R. Torrance, C. O'Connell, "Single Chip Frame Buffer and Graphics Accelerator", US Pat. RE37,944
- P.Gillingham, B.Millar, “High Bandwidth Memory Interface”, US Pat. 6,510,503
- P.Gillingham, A.Ahmed, “Searchline Control Circuit and Power Reduction Method”, US Pat. 6,522,596
- S.Takeda, T.Ema, P.Gillingham, “Memory-Logic Semiconductor Device”, US Pat. 6,529,397
- P.Gillingham, “Read/Write Timing for Maximum Utilization of Bidirectional Read/Write Bus”, US Pat. 6,546,476
- R.Foss, P.Gillingham, R.Harland, V.Lines, "Boosted Voltage Supply ", US Pat. 6,580,654
- J.Kim, P.Vlasenko, D.Perry, P.Gillingham, “Low Power Content Addressable Memory Architecture”, US Pat. 6,584,003
- R.Foss, P.Gillingham, R.Harland, V.Lines, "Dynamic Random Access Memory Boosted Voltage Supply ", US Pat. 6,614,705
- R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 6,657,918
- R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 6,657,919
- P.Gillingham, “Circuit and Method for Performing Variable Width Searches in a Content Addressable Memory”, US Pat. 6,708,250
- P.Gillingham, A.Ahmed, “Searchline Control Circuit and Power Reduction Method”, US Pat. 6,744,688
- P.Gillingham, A.Roth, “Circuit and Method for Reducing Power Usage in a Content Addressable Memory”, US Pat. 6,768,659
- P.Gillingham, B.Millar, “High Bandwidth Memory Interface”, US Pat. 6,779,097
- R.Foss, P.Gillingham, R.Harland, V.Lines, "DRAM Boosted Voltage Supply ", US Pat. 6,980,448
- S.Ma, P.Ma, V.Lines, P.Gillingham, R.McKenzie, A.Ahmed, “Matchline Sense Circuit and Method”, US Pat. 6,987,682
- R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 6,992,950
- D.Perry, P.Gillingham, “Ternary CAM Cell for Reduced Matchline Capacitance”, US Pat. 7,120,040
- S.Ma, P.Ma, V.Lines, P.Gillingham, R.McKenzie, A.Ahmed, “Matchline Sense Circuit and Method”, US Pat. 7,251,148
- P.Gillingham, B.Millar, “High Bandwidth Memory Interface”, US Patent 7,299,330
- D.Perry, P.Gillingham, “Compare Circuit for a Content Addressable Memory Cell”, US Pat. 7,304,876
- P.Gillingham, “Method of Multi-Level Storage in DRAM and Apparatus Thereof”, US Pat. RE40,075
- D. Brown, P.Gillingham, “Dense Mode Coding Scheme”, US Pat. 7,346,009
- D. Fielder, J. Derbyshire, P.Gillingham, R. Torrance, C. O'Connell, "Single Chip Frame Buffer and Graphics Accelerator", US Pat. RE40,326
- S.Ma, P.Ma, V.Lines, P.Gillingham, R.McKenzie, A.Ahmed, “Matchline Sense Circuit and Method”, US Pat. 7,382,638
- R.Foss, P.Gillingham, R.Harland, M.Mitsuhashi, A.Wada, "Dynamic Random Access Memory Using Imperfect Isolating Transistors", US Pat. RE40,552
- D.Perry, P.Gillingham, “Compare Circuit for a Content Addressable Memory Cell”, US Pat. 7,561,454
- R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 7,599,246
- D. Brown, P.Gillingham, “Dense Mode Coding Scheme”, US Pat. 7,633,960
- J.Kim, P.Gillingham, “Non-volatile Semiconductor Memory having Multiple External Power Supplies”, US Pat. 7,639,540
- P. Gillingham, R. McKenzie, “Synchronous Memory Read Data Capture”, US Pat. 7,685,393
- P.Gillingham, B.Millar, “Apparatuses for Synchronous Transfer of Information”, US Pat. 7,765,376
- D. Fielder, J. Derbyshire, P.Gillingham, R. Torrance, C. O'Connell, "Single Chip Frame Buffer and Graphics Accelerator", US Pat. RE41,565
- P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 7,885,140
- D. Brown, P.Gillingham, "Dense Mode Coding Scheme”, US Pat. 8,023,519
- P.Gillingham, "Termination Circuit for On-Die Termination”, US Pat. 8,063,658
- P. Gillingham, R. McKenzie, “Synchronous Memory Read Data Capture”, US Pat. 8,086,813
- P.Gillingham, "Reduced Pin Count Interface”, US Pat. 8,122,202
- J.Kim, P.Gillingham, “Non-volatile Semiconductor Memory having Multiple External Power Supplies”, US Pat. 8,194,456
- P.Gillingham, B.Millar, “High Bandwidth Memory Interface”, US Patent 8,250,297
- P.Gillingham, B.Millar, “High Bandwidth Memory Interface”, US Patent 8,266,372
- J.Kim, P.Gillingham, “Non-volatile Semiconductor Memory having Multiple External Power Supplies”, US Pat. 8,300,471
- R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 8,369,182
- P.Gillingham, “Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking”, US Patent 8,400,781
- J.Kim, P.Gillingham, W.Petrie, "Phase-Change Memory with Multiple Polarity Bits Having Enhanced Endurance and Error Tolerance”, US Pat. 8,432,729
- P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 8,432,767
- P.Gillingham, "Termination Circuit for On-Die Termination”, US Pat. 8,471,591
- P.Gillingham, "Multi-Chip Package with Offset Die Stacking”, US Pat. 8,502,368
- P.Gillingham, R.Schuetz, "Configurable Module and Memory Subsystem”, US Pat. 8,503,211
- H.Pyeon, H.Jung, P.Gillingham, "Bridging Device Having a Frequency Configurable Clock Domain”, US Pat. 8,504,789
- P.Gillingham, "Simultaneous Read and Write Data Transfer”, US Pat. 8,521,980
- H.Pyeon, J.Kim, P.Gillingham, "Bridging Device Having a Configurable Virtual Page Size”, US Pat. 8,549,209
- D. Fielder, J. Derbyshire, P.Gillingham, R. Torrance, C. O'Connell, "Single Chip Frame Buffer and Graphics Accelerator", US Pat. RE44,589
- J.Kim, P.Gillingham, “Non-volatile Semiconductor Memory having Multiple External Power Supplies”, US Pat. 8,619,473
- P.Gillingham, "Method and Apparatus for Sharing Internal Power Supplies in Integrated Circuit Devices”, US Pat. 8,625,352
- R.Foss, P.Gillingham, G.Allan, "Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory", US Pat. 8,638,638
- P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 8,644,108
- P.Gillingham, B.Millar, “High Bandwidth Memory Interface”, US Pat. 8,654,573
- P.Gillingham, “Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking”, US Pat. 8,711,573
- P.Gillingham, R.Schuetz, "Configurable Module and Memory Subsystem”, US Pat. 8,767,430
- J.Kim, P.Gillingham, W.Petrie, "Phase-Change Memory with Multiple Polarity Bits Having Enhanced Endurance and Error Tolerance”, US Pat. 8,780,622
- H.Pyeon, P.Gillingham, "Clock Reproducing and Timing Method in a System Having a Plurality of Devices”, US Pat. 8,781,053
- P.Gillingham, "Reduced Pin Count Interface”, US Pat. 8,825,966
- P.Gillingham, "Interposer for Stacked Semiconductor Devices”, US Pat. 8,836,148
- P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 8,854,915
- P.Gillingham, "Error Detection Method and System Including One or More Memory Device”, US Pat. 8,880,970
- P.Gillingham, "Simultaneous Read and Write Data Transfer”, US Pat. 8, 898,415
- P.Gillingham, "Semiconductor Memory Device with Plural Memory Die and Controller Die”, US Pat. 8, 996,208
- P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 9,042,199
- H.Pyeon, P.Gillingham, "Clock Reproducing and Timing Method in a System Having a Plurality of Devices”, US Pat. 9,148,277
- P.Gillingham, "Multi-Chip Package with Offset Die Stacking”, US Pat. 9,177,863
- P.Gillingham, “Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking”, US Pat. 9,190,369
- P.Gillingham, “Method and Apparatus for Sharing Internal Power Supplies in Integrated Circuit Devices”, US Pat. 9,236,095
- J.Kim, P.Gillingham, “Non-volatile Semiconductor Memory having Multiple External Power Supplies”, US Pat. 9,245,640
- P.Gillingham, "Semiconductor Memory Device with Plural Memory Die and Controller Die”, US Pat. 9,348,786
- P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 9,384,847
- P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 9,552,889
- J.Kim, P.Gillingham, “Non-volatile Semiconductor Memory having Multiple External Power Supplies”, US Pat. 9,576,675
- P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 9,740,407
- P.Gillingham, “Using Interrupted Through-Silicon-Vias in Integrated Circuits Adapted for Stacking”, US Pat. 9,780,073
- J.Kim, P.Gillingham, “Non-volatile Semiconductor Memory having Multiple External Power Supplies”, US Pat. 9,928,918
- P.Gillingham, R.McKenzie, “Synchronous Memory Read Data Capture”, US Pat. RE46,819
- P.Gillingham, G.Allan, "Clock Mode Determination in a Memory System”, US Pat. 9,971,518
- H.Pyeon, J.Kim, P.Gillingham, "Bridging Device Having a Configurable Virtual Page Size”, US Pat. 9,977,731
|